There are a widespread variety of flash memories with different cell structures, program/erase methods, and array organizations. Flash memories can be classified into two groups based on their program/erase methods: (1) employing channel hot electron (CHE) injection for programming and employing Fowler-Nordheim (FN) tunneling for erasing; and (2) employing Fowler-Nordheim (FN) tunneling for both programming and erasing.
Method (1) is the most common method for flash memories, and particularly for ETOX (EPROM Tunnel Oxide) type flash memories. The CHE program consumes more than 300 μA per cell, hence only a few bits can be programmed at a time by an on-chip charge pump. To improve the hot electron generation efficiency, the drain junction needs to be an abrupt junction, and sometimes covered by a p+ region to enhance the impact ionization.
The FN tunneling can be divided into source/drain edge FN tunneling and channel FN tunneling. The edge FN tunneling is to extract electrons from the floating gate (FG) by applying a negative voltage (e.g. −10 V) to the control gate (CG) and a positive voltage (e.g. 5 V) to the source or drain junction. The source or drain junction needs to be a lighter and deeper junction to (a) sustain a high voltage without breakdown, (b) reduce the band-to-band tunneling (BBT) current, (c) reduce the hot hole injection, and (d) increase the overlap area with the floating gate. The edge FN tunneling consumes about 10 nA per cell, which is mostly constituted of the substrate leakage current due to the band-to-band tunneling.
All the memory cells relying on the edge effects (such as edge program and edge erase) require process optimization on the source/drain junctions to enhance the program/erase efficiencies. Such process optimization normally results in asymmetric source/drain junctions, which adds more complexity to the manufacturing process. Moreover, the endurance characteristics of the memory cells employing the edge program and/or edge erase are deteriorated with repeated program/erase cycles due to the trapped electron and/or holes in the tunnel oxide.
The FN tunneling via the channel region consumes the least current, in the order of 10 pA per cell, among all program and erase mechanisms. Therefore, a large number of flash cells can be programmed and erased simultaneously by the on-chip charge pumps, which can be also smaller than the charge pumps used for edge program and edge erase. The memory cell employing uniform channel program and channel erase also shows the least deterioration in the endurance characteristics because the trapped carriers are neutralized by the alternative electric fields. Since the memory cell does not rely on the source/drain edge in program or erase, the source/drain junctions can be symmetric, which help to simplify the fabrication process.
The physical dimensions of CMOS devices will be continuously scaled down in the future semiconductor technologies. The device dimensions of memory cells also need to be scaled down in the future flash memory technologies. Many of the challenges for bulk CMOS devices can be relaxed if the devices are fabricated on silicon-on insulator (SOI) wafers. A SOI flash memory technology has been proposed in U.S. Pat. No. 5,796,142 and U.S. Pat. No. 5,885,868 to achieve the goals of high density and low power consumption. The memory cell employs channel program and channel erase, which consume very low currents. The memory cell has a symmetric device structure. The memory cells are arranged in a NOR-type contactless flash memory array. Every two adjacent columns share the source/drain line in between. There is no field oxide within a memory array. The memory cell size (about 4 F2) is indeed very small, only about one third of a typical ETOX cell size (about 12 F2).
Detailed disclosures in U.S. Pat. No. 5,796,142 and U.S. Pat. No. 5,885,868 are now discussed. FIG. 1 schematically shows the flash memory cell structure of U.S. Pat. No. 5,796,142 and U.S. Pat. No. 5,885,868. The memory cells are fabricated on a SOI wafer, which consists of a silicon substrate 10, an oxide layer 11, and a p-type doped silicon thin film. Each of the memory cell transistor is constituted of a tunnel oxide film 12, a first polysilicon (poly-1) floating gate 13, an oxide-nitride-oxide (ONO) insulating film 14, and a second polysilicon (poly-2) control gate (CG) 15. The n+ source/drain are formed by arsenic implantation into the p-type silicon thin film after the poly-1 floating gate 13 is patterned. The n+ source/drain is shared between two adjacent cells.
FIG. 2 is a circuit diagram showing the memory array portion of the flash memory device disclosed in U.S. Pat. No. 5,796,142 and U.S. Pat. No. 5,885,868. The source lines and the drain lines are shared between two adjacent columns. The body line (e.g. BLm) of each column is isolated from the body lines (e.g. BLm−1 and BLm+1) of adjacent columns by the n+ source/drain lines and the oxide layer 11 beneath the p-type body.
Memory cell program, erase, and read bias configurations are summarized in TABLE 1. Both program and erase cell operations are accomplished by the Fowler-Nordheim (FN) tunneling effect between the floating gate and the body. It is known that the FN tunneling current is much smaller than the hot-electron injection (HEI) current by orders of magnitude. FIG. 3a shows the cross section view of the program operation of a memory cell. To program a memory cell, a positive high voltage (e.g. 13 V) is applied to the word line and a negative high voltage (e.g. −7 V) is applied to the body line. According to the descriptions of the prior art, the memory cell is programmed by charging up the floating gate. The floating gate potential is coupled to the control gate voltage and the body voltage through the CG-to-FG and body-to-FG coupling coefficients. A voltage difference is therefore created between the floating gate and the body. Electrons are injected from the transistor body to the floating gate through the tunnel oxide by the Fowler-Nordheim tunneling effect. According to the suggested programming condition, the breakdown voltage of the source/drain-to-body junctions needs to be larger than 7 V. Such a large breakdown voltage imposes a serious limitation to scale down the physical dimensions of the memory cell for the future technologies.
TABLE 1ProgramEraseReadWL13 V−13 VVddBL −7 V     7 V0 VSL 0 VFloating0 VDL 0 VFloating1 V
However, an inversion layer is formed in the semiconductor surface when a positive high voltage is applied to the control gate in the program operation. In fact, channel regions are formed in all the memory cells along the selected word line. All the channel regions are connected because adjacent memory cells share the source/drain lines in between. The source/drain voltage is 0 V for the selected and unselected memory cells in the program operation. All the channel potentials are the same, i.e. 0V, for both selected and unselected memory cells along the selected word line. U.S. Pat. No. 5,796,142 and U.S. Pat. No. 5,885,868 therefore cannot properly perform the program operation. The inversion layer shields the body potential from the floating gate. The body potential has no effect in programming the cell. The formation of inversion layers in the program operation is not taken into consideration in U.S. Pat. No. 5,796,142 and U.S. Pat. No. 5,885,868.
FIG. 3b shows the cross section view of the erase operation of a memory cell. To erase a memory cell, a negative high voltage (e.g. −13 V) is applied to the word line and a positive high voltage (e.g. 7 V) is applied to the body line. The source and drain are floating. The floating source and drain will be charged up by the positively biased p-type body. Because the control gate is negatively biased, the semiconductor surface is in the accumulation region. The floating gate potential is coupled to the control gate voltage and the body voltage through the CG-to-FG and body-to-FG coupling coefficients. A voltage difference is therefore created across the tunnel oxide. Electrons are removing from the floating gate to the transistor body through the tunnel oxide by the Fowler-Nordheim tunneling effect.
FIG. 4 is a layout plan view showing the memory array portion of the U.S. Pat. No. 5,796,142 and U.S. Pat. No. 5,885,868 of the prior art. The field oxide 40 provides the device isolation between two adjacent memory array blocks, and between the memory array block and outside peripheral circuitry. There is no field oxide inside the memory array block. The poly-1 layer 41 defines the p-type body regions. The n+ source/drain area 42 is implanted after patterning the poly-1 41. The poly-2 layer 43 defines the word lines. The intersection of the poly-1 layer 41 and the poly-2 layer 43 defines the floating gate 46. The n+ contact 44 provided an electric contact to the n+ source/drain area. The body contact 45 provided an electric contact to the p-type body area. The size of the unit cell 47 is very small, which is about 4 F2 where F is the minimum geometry feature. The small memory cell size is achieved because adjacent memory cell columns share the source/drain line in between and there is no field oxide inside the memory array block.
FIG. 5a is the cross-sectional view taken along line 4A–4A′ of FIG. 4. FIG. 5b is a cross-sectional view taken along line 4B–4B′ of FIG. 4. The starting material is a p-type SOI wafer, which consists of a p-type doped silicon thin film, an oxide layer 51, and a silicon substrate 50. A layer of tunnel oxide layer 52 is grown on the SOI wafer, after which a first polysilicon layer 53 is deposited and patterned, followed by arsenic implantation to form the n+ source/drain lines. A first boron phosphosilicate glass (BPSG) layer 54 is deposited, followed by reflow and etch back. An ONO layer 55 is formed. A second polysilicon layer 56 is then deposited. Stacked gates are formed by removing the unwanted poly-2 56, ONO 55, and poly-1 53 layers. A second BPSG layer 57 is then deposited to cover the stack gates. Contact openings for the source/drain lines 42, body lines 41, and word lines 43 are formed. Metal lines 58 leading to the contact openings are formed for connecting the memory cells with peripheral circuits.
For the device structure in FIG. 5a, the floating gate has the same coupling areas to the control gate and to the body, but the effective oxide thickness of the ONO layer 55 is thicker than the thickness of the tunnel oxide 52. The CG-to-FG coupling ratio is below 50%, which is smaller than the coupling ratios of most NOR-type flash technologies. The program/erase voltages must be high enough to compensate the low CG-to-FG coupling ratio. The coupling ratio of a typical ETOX flash memory cell is about 65%. The floating gate usually extends beyond the active area, which is called FG wing, to increase the coupling ratio.
The original goal of the U.S. Pat. No. 5,796,142 and U.S. Pat. No. 5,885,868 was to provide a solution to the low-power and high-density flash memory. The cell program/erase (P/E) operations are uniform FN channel program and uniform FN channel erase. The cell size is impressively small, i.e. 4 F2, which is about one third of the cell size of a typical ETOX memory cell (about 12 F2). Unfortunately, the flash memory device in U.S. Pat. No. 5,796,142 and U.S. Pat. No. 5,885,868 do not work as it is intended to because the inversion layer is induced in the programming phase. In addition, the prior art device also undesirably requires large breakdown voltage of source/drain-to-body junctions and large program/erase voltages due to the low CG-to-FG coupling ratio.